Performance Analysis of High Speed Cmos Full Adder Circuit for Low Voltage Vlsi Circuit Design in Nanometer

http: // www.ijrsm.com © International Journal of Research Science & Management [48] PERFORMANCE ANALYSIS OF HIGH SPEED CMOS FULL ADDER CIRCUIT FOR LOW VOLTAGE VLSI CIRCUIT DESIGN IN NANOMETER Anuj Dev & Sandip Nimade Technocrats Institute of Technology Bhopal, India DOI: 10.5281/zenodo.569383 Abstract As the technology scaling reduces the gate oxide thickness and the gate length thereby increasing the transistor density and also reduces the delay. Reduced gate lengths result in an increase in the leakage power dissipation.. Power optimization is also important for many designs to minimize package cost and maximize battery back-up of system. Power optimization is possible at each level of design process from higher architecture level to lower physical level. In this paper we have compared some existing Adder circuit designs for power consumption, delay, PDP at different frequencies viz 10 MHz, 200 MHz and 1 GHz. Simulations are performed by using Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed to verify the existing designs. Maximum saving of power is at low frequency by Hybrid GDI adder circuit is 96.3% with respect to C-CMOS and significant improvement is observed at other frequencies also. Hybrid GDI needs less number of transistors as compared to standard CMOS technique. Need of less transistors leads to low cost of device.